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| freescale semiconductor data sheet: advance information document number: MPC5604Bc rev. 8, 11/2010 ? freescale semiconductor, inc., 2009, 2010. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MPC5604B/c tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm 208 mapbga (17 x 17 x 1.7 mm) 144 lqfp (20 x 20 x 1.4 mm) 100 lqfp (14 x 14 x 1.4 mm) 64 lqfp (10 x 10 x 1.4 mm) 32-bit mcu family built on the power architecture ? for automotive body electr onics applications features ? single issue, 32-bit cpu core complex (e200z0) ? compliant with the power architecture ? embedded category ? includes an instruction set enhancement allowing variable length encoding (vle) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 512 kb on-chip code flash supported with the flash controller ? 64 (4 16) kb on-chip data flash memory with ecc ? up to 48 kb on-chip sram ? memory protection unit (mpu) with 8 region descriptors and 32-byte region granularity ? interrupt controller (intc) with 148 interrupt vectors, including 16 exte rnal interrupt sources and 18 external interrupt/wakeup sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? boot assist module (bam) supports internal flash programming via a serial link (can or sci) ? timer supports input/output channels providing a range of 16-bit input captu re, output compare, and pulse width modulation functions (emios-lite) ? 10-bit analog-to-digital converter (adc) ? 3 serial peripheral interface (dspi) modules MPC5604B/c microcontroller data sheet 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 35 4.5 recommended operating conditions . . . . . . . . . . . . . . 36 4.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . 40 4.8 reset electrical characteristics . . . . . . . . . . . . . . . . . 51 4.9 power management electrical characteristics . . . . . . . 53 4.10 low voltage domain power consumption . . . . . . . . . . . 56 4.11 flash memory electrical characteristics . . . . . . . . . . . . 58 4.12 electromagnetic compatibility (emc) characteristics . . 62 4.13 fast external crystal oscillator (4 to 16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.14 slow external crystal o scillator (32 kh z) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.15 fmpll electrical characteristics. . . . . . . . . . . . . . . . . . 69 4.16 fast internal rc oscill ator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.17 slow internal rc osci llator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.18 adc electrical characteristics. . . . . . . . . . . . . . . . . . . . 72 4.19 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.1 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 89 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 100
MPC5604B/c microcontrolle r data sheet, rev. 8 introduction freescale semiconductor 2 ? up to 4 serial communicati on interface (linflex) modules ? up to 6 enhanced full can (flexcan) modules with configurable buffers ? 1 inter ic communication interface (i 2 c) module ? up to 123 configurable general purpose pins suppo rting input and output operations (package dependent) ? real time counter (rtc) with clock source from 128 khz or 16 mhz internal rc oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds ? up to 6 periodic interrupt timers (pit) with 32-bit counter resolution ? 1 system module timer (stm) ? nexus development interface (ndi) per i eee-isto 5001-2003 class two plus standard ? device/board boundary scan testing supported with per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vre g) for regulation of input supply for all internal levels 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. to ensure a complete understa nding of the device functionality, refer al so to the device reference manual and errata sheet. 1.2 description the MPC5604B/c is a family of next generation microcontrollers built on the power architecture ? embedded category. the MPC5604B/c family of 32-bit microcontrollers is the latest achievement in integrated auto motive application controllers. it belongs to an expanding family of automotive-focused produc ts designed to address the next wave of body electronics applications within the vehicle. the advanced and cost-efficient host processo r core of this automotive controller family complies with the power architecture embedded category and only implements th e vle (variable-lengt h encoding) apu, providing improved code density. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, op erating systems and configuration code to assist with users implementations. MPC5604B/c microcontrolle r data sheet, rev. 8 introduction freescale semiconductor 3 table 1. MPC5604B/c device comparison 1 feature device mpc56 02bxlh mpc56 02bxll mpc56 02bxlq mpc56 02cxlh mpc56 02cxll mpc56 03bxlh mpc56 03bxll mpc56 03bxlq mpc56 03cxlh mpc56 03cxll mpc56 04bxlh mpc56 04bxll mpc56 04bxlq mpc56 04cxlh mpc56 04cxll mpc560 4bxmg cpu e200z0h execution speed 2 static ? up to 64 mhz code flash 256 kb 384 kb 512 kb data flash 64 kb (4 16 kb) ram 24kb 32kb 28kb 40kb 32kb 48 kb mpu 8-entry adc 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit ctu ye s total timer i/o 3 emios 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit ? pwm + mc + ic/oc 4 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch ? pwm + ic/oc 4 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch ?ic/oc 4 0ch 3ch 6ch 0ch 3ch 0ch 3ch 6ch 0ch 3ch 0ch 3ch 6ch 0ch 3ch 6ch sci (linflex) 3 5 4 spi (dspi) 2 3 2 3 2 3 2 3 2 3 2 3 can (flexcan) 2 6 56 3 7 56 3 7 56 i 2 c 1 32 khz oscillator ye s gpio 8 45 79 123 45 79 45 79 123 45 79 45 79 123 45 79 123 debug jtag nexus2+ MPC5604B/c microcontrolle r data sheet, rev. 8 introduction freescale semiconductor 4 package 64 lqfp 9 100 lqfp 144 lqfp 64 lqfp 9 100 lqfp 64 lqfp 9 100 lqfp 144 lqfp 64 lqfp 9 100 lqfp 64 lqfp 9 100 lqfp 144 lqfp 64 lqfp 9 100 lqfp 208 mapbg a 10 1 feature set dependent on selected peripheral mu ltiplexing?table shows example implementation 2 based on 125 c ambient operating temperature 3 refer to emios section of device reference manual for information on the channel configuration and functions 4 ic - input capture; oc - output compare; pwm - pulse width modulation; mc - modulus counter 5 sci0, sci1 and sci2 are availa ble. sci3 is not available. 6 can0, can1 are available. can2, can3, can4 and can5 are not available. 7 can0, can1 and can2 are available. can3, can4 and can5 are not available. 8 i/o count based on multiplexing with peripherals 9 all 64 lqfpinformation is indicative and mu st be confirmed during silicon validation. 10 208 mapbga available only as development package for nexus2+ table 1. MPC5604B/c device comparison 1 (continued) feature device mpc56 02bxlh mpc56 02bxll mpc56 02bxlq mpc56 02cxlh mpc56 02cxll mpc56 03bxlh mpc56 03bxll mpc56 03bxlq mpc56 03cxlh mpc56 03cxll mpc56 04bxlh mpc56 04bxll mpc56 04bxlq mpc56 04cxlh mpc56 04cxll mpc560 4bxmg block diagram MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 5 2 block diagram figure 1 shows a top-level block diagram of the MPC5604B/c device series. figure 1. MPC5604B/c series block diagram 3 x dspi fmpll nexus 2+ nexus sram siul reset control 48 kb external imux gpio and jtag pad control jtag port nexus port e200z0h interrupt requests 64-bit 2 x 3 crossbar switch 6 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc i 2 c . . . 4 x linflex 2 x emios 36 ch. adc mpu cmu sram flash code flash 512 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module flexcan controller area network cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) ecsm error correction status module mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nexus nexus development interface (ndi) level nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit mpu ecsm from peripheral registers blocks wkpu interrupt request with wakeup functionality MPC5604B/c microcontrolle r data sheet, rev. 8 block diagram freescale semiconductor 6 table 2 summarizes the functions of all blocks present in the mp c5604b/c series of microcontrollers. please note that the presence and number of blocks varies by device and package. table 2. MPC5604B/c series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to digital-converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configurat ion and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors re ported by error-correcting codes enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modulated phase-locked loop) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load clock generation module (mc_cgm) provides logic and contro l required for the generatio n of system and peripheral clocks mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional st ates; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device block diagram MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 7 memory protection unit (mpu) provides hardware access control for all memory references generated in a device nexus development interface (ndi) provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard periodic interrupt timer (pit) produces periodic interrupts and triggers real-time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) system integration unit (siu) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration static random-access memory (sram) provides storage for program code, constants, and variables system status configuration module (sscm) provides system configurati on and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) the wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. crossbar (xbar) switch supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width table 2. MPC5604B/c series block summary (continued) block function MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 8 3 package pinouts and signal descriptions 3.1 package pinouts the available lqfp pinouts and the 208 mapbga ballmap are provided in the following figures. for pin signal descriptions, please refer to the device reference manual. figure 2. lqfp 64-pin configuration (top view) 1 figure 3. lqfp 64-pin configuration 5can 4lin (top view) 2 1. all 64 lqfpinformation is indicative and must be confirmed during silicon validation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa [ 2 ] pa [ 1 ] pa [ 0 ] vpp_test vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pa [ 3 ] pb[15] pb[14] pb[13] pb[12] pb[11] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] 64 lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa [ 2 ] pa [ 1 ] pa [ 0 ] vpp_test vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pf[14] pf[15] pg[0] pg[1] pa [ 3 ] pb[15] pb[14] pb[11] pb[7] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] 64 lqfp package pinouts and signal descriptions MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 9 figure 4. lqfp 100-pin configuration (top view) 2. all 64 lqfpinformation is indicative and must be confirmed during silicon validation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] 100 lqfp note: availability of port pin alternate functions depends on product selection. MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 10 figure 5. lqfp 144-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pf[10] pf[11] pa [ 1 5 ] pf[13] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] 144 lqfp note: availability of port pin alternate functions depends on product selection. package pinouts and signal descriptions MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 11 3.2 pin muxing table 3 defines the pin list and muxing for this device. each entry of table 3 shows all the possible configura tions for each pin, via the altern ate functions. the default function assigned to each pin after reset is indicated by af0. 1 2 3 4 5 6 7 8 9 10111213141516 a pc[8] pc[13] nc nc ph[8] ph[4] pc[5] pc[0] nc nc pc[2] nc pe[15] nc nc nc a b pc[9] pb[2] nc pc[12] pe[6] ph[5] pc[4] ph[9] ph[10] nc pc[3] pg[11] pg[15] pg[14] pa[11] pa[10] b c pc[14] vdd_hv pb[3] pe[7] ph[7] pe[5] pe[3] vss_lv pc[1] nc pa[5] nc pe[14] pe[12] pa[9] pa[8] c d nc nc pc[15] nc ph[6] pe[4] pe[2] vdd_lv vdd_hv nc pa[6] nc pg[10] pf[14] pe[13] pa[7] d e pg[4] pg[5] pg[3] pg[2] pg[1] pg[0] pf[15] vdd_hv e f pe[0] pa[2] pa[1] pe[1] ph[0] ph[1] ph[3] ph[2] f g pe[9] pe[8] pe[10] pa[0] vss_hv vss_hv vss_hv vss_hv vdd_hv nc nc mseo g h vss_hv pe[11] vdd_hv nc vss_hv vss_hv vss_hv vss_hv mdo3 mdo2 mdo0 mdo1 h j reset vss_lv nc nc vss_hv vss_hv vss_hv vss_hv nc nc nc nc j k evti nc vdd_bv vdd_lv vss_hv vss_hv vss_hv vss_hv nc pg[12] pa[3] pg[13] k l pg[9] pg[8] nc evto pb[15] pd[15] pd[14] pb[14] l m pg[7] pg[6] pc[10] pc[11] pb[13] pd[13] pd[12] pb[12] m n pb[1] pf[9] pb[0] nc nc pa[4] vss_lv extal vdd_hv pf[0] pf[4] nc pb[11] pd[10] pd[9] pd[11] n p pf[8] nc pc[7] nc nc pa[14] vdd_lv xtal pb[10] pf[1] pf[5] pd[0] pd[3] vdd_hv _adc pb[6] pb[7] p r pf[12] pc[6] pf[10] pf[11] vdd_hv pa[15] pa[13] nc osc32k _xtal pf[3] pf[7] pd[2] pd[4] pd[7] vss_hv _adc pb[5] r t nc nc nc mcko nc pf[13] pa[12] nc osc32k _extal pf[2] pf[6] pd[1] pd[5] pd[6] pd[8] pb[4] t 1 2 3 4 5 6 7 8 9 10111213141516 note: 208 mapbga available only as development package for nexus 2+. nc = not connected figure 6. 208 mapbga configuration MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 12 table 3. functional port pin descriptions port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout ? wkup[19] 4 siul emios0 cgl ? wkpu i/o i/o o ? i m tristate 5 5 12 16 g4 pa[1] pcr[1] af0 af1 af2 af3 ? ? gpio[1] e0uc[1] ? ? nmi 5 wkup[2] 4 siul emios0 ? ? wkpu wkpu i/o i/o ? ? i i s tristate 4 4 7 11 f3 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ? wkup[3] 4 siul emios0 ? ? wkpu i/o i/o ? ? i stristate3359f2 pa[3] pcr[3] af0 af1 af2 af3 ? gpio[3] e0uc[3] ? ? eirq[0] siul emios0 ? ? siul i/o i/o ? ? i stristate43396890k15 pa[4] pcr[4] af0 af1 af2 af3 ? gpio[4] e0uc[4] ? ? wkup[9] 4 siul emios0 ? ? wkpu i/o i/o ? ? i stristate20202943n6 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] ? ? siul emios0 ? ? i/o i/o ? ? mtristate515179118c11 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 13 pa[6] pcr[6] af0 af1 af2 af3 ? gpio[6] e0uc[6] ? ? eirq[1] siul emios0 ? ? siul i/o i/o ? ? i stristate525280119d11 pa[7] pcr[7] af0 af1 af2 af3 ? gpio[7] e0uc[7] lin3tx ? eirq[2] siul emios0 linflex_3 ? siul i/o i/o o ? i stristate444471104d16 pa[8] pcr[8] af0 af1 af2 af3 ? n/a 6 ? gpio[8] e0uc[8] ? ? eirq[3] abs[0] lin3rx siul emios0 ? ? siul bam linflex_3 i/o i/o ? ? i i i s input, weak pull-up 45 45 72 105 c16 pa[9] pcr[9] af0 af1 af2 af3 n/a 6 gpio[9] e0uc[9] ? ? fab siul emios_0 ? ? bam i/o i/o ? ? i spull- down 46 46 73 106 c15 pa[10] pcr[10] af0 af1 af2 af3 gpio[10] e0uc[10] sda ? siul emios_0 i2c_0 ? i/o i/o i/o ? stristate474774107b16 pa[11] pcr[11] af0 af1 af2 af3 gpio[11] e0uc[11] scl ? siul emios0 i2c_0 ? i/o i/o i/o ? stristate484875108b15 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 14 pa[12] pcr[12] af0 af1 af2 af3 ? gpio[12] ? ? ? sin_0 siul ? ? ? dspi0 i/o ? ? ? i stristate22223145t7 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 ? ? siul dspi_0 ? ? i/o o ? ? mtristate21213044r7 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 ? eirq[4] siul dspi_0 dspi_0 ? siul i/o i/o i/o ? i mtristate19192842p6 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 ? wkup[10] 4 siul dspi_0 dspi_0 ? wkpu i/o i/o i/o ? i mtristate18182740r6 pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx ? ? siul flexcan_0 ? ? i/o o ? ? mtristate14142331n3 pb[1] pcr[17] af0 af1 af2 af3 ? ? gpio[17] ? ? ? wkup[4] 4 can0rx siul ? ? ? wkpu flexcan_0 i/o ? ? ? i i stristate15152432n1 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 15 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda ? siul linflex_0 i2c_0 ? i/o o i/o ? m tristate 64 64 100 144 b2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] ? scl ? wkup[11] 4 lin0rx siul ? i2c_0 ? wkpu linflex_0 i/o ? i/o ? i i stristate1111c3 pb[4] pcr[20] af0 af1 af2 af3 ? gpio[20] ? ? ? anp[0] siul ? ? ? adc i ? ? ? i itristate32325072t16 pb[5] pcr[21] af0 af1 af2 af3 ? gpio[21] ? ? ? anp[1] siul ? ? ? adc i ? ? ? i i tristate 35 ? 53 75 r16 pb[6] pcr[22] af0 af1 af2 af3 ? gpio[22] ? ? ? anp[2] siul ? ? ? adc i ? ? ? i i tristate 36 ? 54 76 p15 pb[7] pcr[23] af0 af1 af2 af3 ? gpio[23] ? ? ? anp[3] siul ? ? ? adc i ? ? ? i itristate37355577p16 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 16 pb[8] pcr[24] af0 af1 af2 af3 ? ? gpio[24] ? ? ? ans[0] osc32k_xtal 7 siul ? ? ? adc sxosc i ? ? ? i i/o itristate30303953r9 pb[9] pcr[25] af0 af1 af2 af3 ? ? gpio[25] ? ? ? ans[1] osc32k_extal 7 siul ? ? ? adc sxosc i ? ? ? i i/o itristate29293852t9 pb[10] pcr[26] af0 af1 af2 af3 ? ? gpio[26] ? ? ? ans[2] wkup[8] 4 siul ? ? ? adc wkpu i/o ? ? ? i i jtristate31314054p9 pb[11] 8 pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 ans[3] siul emios_0 ? dspi_0 adc i/o i/o ? i/o i jtristate38365981n13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 anx[0] siul emios ? dspi_0 adc i/o i/o ? o i j tristate 39 ? 61 83 m16 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 anx[1] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 40 ? 63 85 m13 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 17 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 anx[2] siul emios0 ? dspi_0 adc i/o i/o ? o i jtristate41376587l16 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 anx[3] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate42386789l13 pc[0] 9 pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 59 59 87 126 a8 pc[1] 9 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo 10 ? siul ? jtagc ? i/o ? o ? mtristate545482121c9 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx 11 ? eirq[5] siul dspi_1 linflex_4 ? siul i/o i/o o ? i mtristate505078117a11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] ? can1rx can4rx 11 eirq[6] siul dspi_1 adc ? flexcan_1 flexcan_4 siul i/o i/o o ? i i i stristate494977116b11 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 18 pc[4] pcr[36] af0 af1 af2 af3 ? ? gpio[36] ? ? ? sin_1 can3rx 11 siul ? ? ? dspi_1 flexcan_3 i/o ? ? ? i i mtristate626292131b7 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx 11 ? eirq[7] siul dspi1 flexcan_3 ? siul i/o o o ? i mtristate616191130a7 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx ? ? siul linflex_1 ? ? i/o o ? ? stristate16162536r2 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? ? ? lin1rx wkup[12] 4 siul ? ? ? linflex_1 wkpu i/o ? ? ? i i stristate17172637p3 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx ? ? siul linflex_2 ? ? i/o o ? ? stristate636399143a1 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? ? ? lin2rx wkup[13] 4 siul ? ? ? linflex_2 wkpu i/o ? ? ? i i stristate2222b1 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 19 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx 11 ma[1] siul flexcan_1 flexcan_4 adc i/o o o o mtristate13132228m3 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ? can1rx can4rx 11 wkup[5] 4 siul ? ? ? flexcan_1 flexcan_4 wkpu i/o ? ? ? i i i s tristate ? ? 21 27 m4 pc[12] pcr[44] af0 af1 af2 af3 ? gpio[44] e0uc[12] ? ? sin_2 siul emios_0 ? ? dspi_2 i/o i/o ? ? i m tristate ? ? 97 141 b4 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate ? ? 98 142 a2 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i s tristate ? ? 3 3 c1 pc[15] pcr[47] af0 af1 af2 af3 gpio[47] e0uc[15] cs0_2 ? siul emios_0 dspi_2 ? i/o i/o i/o ? m tristate ? ? 4 4 d3 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 20 pd[0] pcr[48] af0 af1 af2 af3 ? gpio[48] ? ? ? anp[4] siul ? ? ? adc i ? ? ? i itristate ? ? 41 63 p12 pd[1] pcr[49] af0 af1 af2 af3 ? gpio[49] ? ? ? anp[5] siul ? ? ? adc i ? ? ? i i tristate ? ? 42 64 t12 pd[2] pcr[50] af0 af1 af2 af3 ? gpio[50] ? ? ? anp[6] siul ? ? ? adc i ? ? ? i itristate ? ? 43 65 r12 pd[3] pcr[51] af0 af1 af2 af3 ? gpio[51] ? ? ? anp[7] siul ? ? ? adc i ? ? ? i itristate ? ? 44 66 p13 pd[4] pcr[52] af0 af1 af2 af3 ? gpio[52] ? ? ? anp[8] siul ? ? ? adc i ? ? ? i itristate ? ? 45 67 r13 pd[5] pcr[53] af0 af1 af2 af3 ? gpio[53] ? ? ? anp[9] siul ? ? ? adc i ? ? ? i i tristate ? ? 46 68 t13 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 21 pd[6] pcr[54] af0 af1 af2 af3 ? gpio[54] ? ? ? anp[10] siul ? ? ? adc i ? ? ? i i tristate ? ? 47 69 t14 pd[7] pcr[55] af0 af1 af2 af3 ? gpio[55] ? ? ? anp[11] siul ? ? ? adc i ? ? ? i itristate ? ? 48 70 r14 pd[8] pcr[56] af0 af1 af2 af3 ? gpio[56] ? ? ? anp[12] siul ? ? ? adc i ? ? ? i i tristate ? ? 49 71 t15 pd[9] pcr[57] af0 af1 af2 af3 ? gpio[57] ? ? ? anp[13] siul ? ? ? adc i ? ? ? i itristate ? ? 56 78 n15 pd[10] pcr[58] af0 af1 af2 af3 ? gpio[58] ? ? ? anp[14] siul ? ? ? adc i ? ? ? i itristate ? ? 57 79 n14 pd[11] pcr[59] af0 af1 af2 af3 ? gpio[59] ? ? ? anp[15] siul ? ? ? adc i ? ? ? i it ristate ? ? 58 80 n16 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 22 pd[12] 8 pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? ans[4] siul dspi_0 emios_0 ? adc i/o o i/o ? i jtristate ? ? 60 82 m15 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? ans[5] siul dspi_1 emios_0 ? adc i/o i/o i/o ? i jtristate ? ? 62 84 m14 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? ans[6] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? ? 64 86 l15 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? ans[7] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? ? 66 88 l14 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? can5rx 11 wkup[6] 4 siul emios_0 ? ? flexcan_5 wkpu i/o i/o ? ? i i s tristate ? ? 6 10 f1 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx 11 ? siul emios_0 flexcan_5 ? i/o i/o o ? m tristate ? ? 8 12 f4 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 23 pe[2] pcr[66] af0 af1 af2 af3 ? gpio[66] e0uc[18] ? ? sin_1 siul emios0 ? ? dspi_1 i/o i/o ? ? i m tristate ? ? 89 128 d7 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios0 dspi_1 ? i/o i/o o ? m tristate ? ? 90 129 c7 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios0 dspi_1 ? siul i/o i/o i/o ? i m tristate ? ? 93 132 d6 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc i/o i/o i/o o m tristate ? ? 94 133 c6 pe[6] pcr[70] af0 af1 af2 af3 gpio[70] e0uc[22] cs3_0 ma[1] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? ? 95 139 b5 pe[7] pcr[71] af0 af1 af2 af3 gpio[71] e0uc[23] cs2_0 ma[0] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? ? 96 140 c4 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx 12 e0uc[22] can3tx 11 siul flexcan_2 i/o flexcan_3 i/o o emios0 o m tristate ? ? 9 13 g2 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 24 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkup[7] 4 can2rx 12 can3rx 11 siul ? emios_0 ? wkpu flexcan_2 flexcan_3 i/o ? i/o ? i i i s tristate ? ? 10 14 g1 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 ? eirq[10] siul linflex_3 dspi_1 ? siul i/o o o ? i s tristate ? ? 11 15 g3 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] ? cs4_1 ? lin3rx wkup[14] 4 siul ? dspi_1 ? linflex_3 wkpu i/o ? o ? i i s tristate ? ? 13 17 h2 pe[12] pcr[76] af0 af1 af2 af3 ? ? gpio[76] ? e1uc[19] 13 ? sin_2 eirq[11] siul ? emios_1 ? dspi_2 siul i/o ? i/o ? i i s tristate ? ? 76 109 c14 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? ? ? 103 d15 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i s tristate ? ? ? 112 c13 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 25 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? ? ? 113 a13 pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? ans[8] siul emios_0 dspi_1 ? adc i/o i/o o ? i j tristate ? ? ? 55 n10 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? ans[9] siul emios_0 dspi_1 ? i i/o i/o o ? i j tristate ? ? ? 56 p10 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? ans[10] siul emios_0 dspi_2 ? adc i/o i/o i/o ? i j tristate ? ? ? 57 t10 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? ans[11] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? ? 58 r10 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0 uc[14] cs2_2 ? ans[12] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? ? 59 n11 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 26 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? ans[13] siul emios_0 dspi_2 ? adc i/o i/o o ? i j tristate ? ? ? 60 p11 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] ? ? ans[14] siul emios_0 ? ? adc i/o i/o ? ? i j tristate ? ? ? 61 t11 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? ? ? ans[15] siul ? ? ? adc i/o ? ? ? i j tristate ? ? ? 62 r11 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx 14 cs4_0 can2tx 15 siul flexcan_3 dspi_0 flexcan_2 i/o o o o m tristate ? ? ? 34 p1 pf[9] pcr[89] af0 af1 af2 af3 ? ? gpio[89] ? cs5_0 ? can2rx 15 can3rx 14 siul ? dspi_0 ? flexcan_2 flexcan_3 i/o ? o ? i i s tristate ? ? ? 33 n2 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] ? ? ? siul ? ? ? i/o ? ? ? m tristate ? ? ? 38 r3 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 27 pf[11] pcr[91] af0 af1 af2 af3 ? gpio[91] ? ? ? wkup[15] 4 siul ? ? ? wkpu i/o ? ? ? i s tristate ? ? ? 39 r4 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 35 r1 pf[13] pcr[93] af0 af1 af2 af3 ? gpio[93] e1uc[26] ? ? wkup[16] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i s tristate ? ? ? 41 t6 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx 11 e1uc[27] can1tx siul flexcan_4 emios_1 flexcan_4 i/o o i/o o m tristate ? 43 ? 102 d14 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] ? ? ? can1rx can4rx 11 eirq[13] siul ? ? ? flexcan_1 flexcan_4 siul i/o ? ? ? i i i s tristate ? 42 ? 101 e15 pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx 11 e1uc[23] ? siul flexcan_5 emios_1 ? i/o o i/o ? m tristate ? 41 ? 98 e14 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 28 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? can5rx 11 eirq[14] siul ? emios_1 ? flexcan_5 siul i/o ? i/o ? i i s tristate ? 40 ? 97 e13 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 8 e4 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] ? ? wkup[17] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i s tristate ? ? ? 7 e3 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 6 e1 pg[5] pcr[101] af0 af1 af2 af3 ? gpio[101] e1uc[14] ? ? wkup[18] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i s tristate ? ? ? 5 e2 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 30 m2 pg[7] pcr[103] af0 af1 af2 af3 gpio[103] e1uc[16] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 29 m1 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 29 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] ? cs0_2 eirq[15] siul emios_1 ? dspi_2 siul i/o i/o ? i/o i s tristate ? ? ? 26 l2 pg[9] pcr[105] af0 af1 af2 af3 gpio[105] e1uc[18] ? sck_2 siul emios1 ? dspi_2 i/o i/o ? i/o s tristate ? ? ? 25 l1 pg[10] pcr[106] af0 af1 af2 af3 gpio[106] e0uc[24] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? ? 114 d13 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? ? 115 b12 pg[12] pcr[108] af0 af1 af2 af3 gpio[108] e0uc[26] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? ? 92 k14 pg[13] pcr[109] af0 af1 af2 af3 gpio[109] e0uc[27] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? ? 91 k16 pg[14] pcr[110] af0 af1 af2 af3 g pio[110] e1uc[0] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? ? 110 b14 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 30 pg[15] pcr[111] af0 af1 af2 af3 gpio[111] e1uc[1] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 111 b13 ph[0] pcr[112] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? ? ? 93 f13 ph[1] pcr[113] af0 af1 af2 af3 gpio[113] e1uc[3] sout1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? ? ? 94 f14 ph[2] pcr[114] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? ? 95 f16 ph[3] pcr[115] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? ? 96 f15 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? ? 134 a6 ph[5] pcr[117] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? ? 135 b6 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 package pinouts and signal descriptions freescale semiconductor 31 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc i/o i/o ? o m tristate ? ? ? 136 d5 ph[7] pcr[119] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? ? 137 c5 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? ? 138 a5 ph[9] 9 pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up ? ? 88 127 b8 ph[10] 9 pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? s input, weak pull-up ? ? 81 120 b9 1 alternate functions are chosen by setting the values of t he pcr.pa bitfields inside the siul module. pcr.pa = 00 -> af0; pcr.pa=01->af1; pcr.pa=10->af2; pcr.pa=11->af3. this is intende d to select the output function s; to use one of the input functions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 multiple inputs are routed to all respective modules internally. the input of some modules must be configured by setting the va lues of the psmio.padselx bi tfields inside the siul module. 3 208 mapbga available only as de velopment package for nexus2+ 4 all wkup pins also support external interrupt capability. see wakeup unit chapter for further details. 5 nmi has higher priority than alternate function. wh en nmi is selected, the pcr.af field is ignored. 6 ?not applicable? because these functions are available only while th e device is booting. refer to bam chapter of the reference manual for details. 7 value of pcr.ibe bit must be 0 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 64 lqfp 5can 4 lin 100 lqfp 144 lqfp 208 map bga 3 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 32 4 electrical characteristics 4.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device logic provide s signals with their respective timing char acteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system must provide signals with their respec tive timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. caution all 64 lqfpinformation is indicative and must be confirmed during silicon validation. 8 this pad is used on mpc5607b 100-pin and 144-pinto provide supply for the second adc. therefore it is recommended not using it to keep the compatibility with the family devices. 9 out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). it is up to the user to configure these pi ns as gpio when ne eded, in this case MPC5604B/c get incompliance with ieee 1149.1-200 1. 10 the tdo pad has been moved into the standby domain in order to allow low-power debug handshaking in standby mode. however, no pull-resistor is active on the tdo pad while in standby mode. at this time the pad is config ured as an input. when no debugg er is connected the tdo pad is floating causing additional current consumption. to avoid the extra c onsumption tdo must be connected. an external pull-up resistor in the range of 47?100 kohms should be added between the tdo pin and vdd. only in case the tdo pin is used as application pin and a pull-up cannot be used then a pul l-down resistor with the same value should be used between td o pin and gnd instead. 11 available only on mpc560xc versions and MPC5604B 208 mapbga devices 12 not available on mpc5602b devices 13 not available in 100 lqfp package 14 available only on MPC5604B 208 mapbga devices 15 not available on mpc5603b 144-pin devices electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 33 4.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 4 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 4.3 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the non-volatile user options register (nvusro) register. table 4. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 34 4.3.1 nvusro[pad3v5v] field description table 5 shows how nvusro[pad3v5v] controls the device configuration. the dc electrical characteristics are dependent on the pad3v5v bit value. 4.3.2 nvusro[oscillator_margin] field description table 6 shows how nvusro[oscillator_margin] controls the device configuration. the fast external crystal oscillator consumptio n is dependent on the osci llator_margin bit value. for a detailed description of the nvusro register , please refer to the MPC5604B/c reference manual. table 5. pad3v5v field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 '1' is delivery value. it is part of shadow flash, thus programmable by customer. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 6. oscillator_margin field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 '1' is delivery value. it is part of shadow flash, thus programmable by customer. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 35 4.4 absolute maximum ratings note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 37 table 9. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max v ss sr digital ground on vss_hv pins ? 0 0 v v dd 1 sr voltage on vdd_hv pins with respect to ground (v ss ) ?4.55.5v voltage drop 2 3.0 5.5 v ss_lv 3 sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_bv 4 sr voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?4 . 5 5 . 5 v voltage drop 2 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v ss_adc sr voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ?v ss ? 0.1 v ss +0.1 v v dd_adc 5 sr voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?4 . 5 5 . 5 v voltage drop 2 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v in sr voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd +0.1 i injpad sr injected input current on any pin during overload condition ? ? 55ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd slope to ensure correct power up 6 ? ? 0.25 v/s t a c-grade part sr ambient temperature under bias f cpu < 64 mhz ? 40 85 c t j c-grade part sr junction temperature under bias ? ? 40 110 t a v-grade part sr ambient temperature under bias f cpu < 64 mhz ? 40 105 t j v-grade part sr junction temperature under bias ? ? 40 130 t a m-grade part sr ambient temperature under bias f cpu < 64 mhz ? 40 125 t j m-grade part sr junction temperature under bias ? ? 40 150 1 100 nf capacitance needs to be provided between each v dd /v ss pair. 2 full device operation is guaranteed by design when the voltage drops below 4.5 v down to 3.0 v. however, certain analog electrical characteristics will not be guaranteed to stay wit hin the stated limits. 3 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4 100 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). 5 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6 guaranteed by device validation MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 38 note ram data retention is guaranteed with v dd_lv not below 1.08 v. 4.6 thermal characteristics 4.6.1 package thermal characteristics table 10. lqfp thermal characteristics 1 symbol c parameter conditions 2 pin count value unit r ? ja cc d thermal resistance, junction-to-ambient natural convection 3 single-layer board - 1s 64 60 c/w 100 64 144 64 four-layer board - 2s2p 64 42 100 51 144 49 r ? jb cc d thermal resistance, junction-to-board 4 single-layer board - 1s 64 24 c/w 100 36 144 37 four-layer board - 2s2p 64 24 100 34 144 35 r ? jc cc d thermal resistance, junction-to-case 5 single-layer board - 1s 64 11 c/w 100 22 144 22 four-layer board - 2s2p 64 11 100 22 144 22 ? jb cc d junction-to-board thermal characterization parameter, natural convection single-layer board - 1s 64 tbd c/w 100 33 144 34 four-layer board - 2s2p 64 tbd 100 34 144 35 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 39 ? jc cc d junction-to-case thermal characterization parameter, natural convection single-layer board - 1s 64 tbd c/w 100 9 144 10 four-layer board - 2s2p 64 tbd 100 9 144 10 1 thermal characteristics are based on simulation. 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to 125 c 3 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 4 junction-to-board thermal resistance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 5 junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. table 10. lqfp thermal characteristics 1 (continued) symbol c parameter conditions 2 pin count value unit MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 40 4.6.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : t j = t a + (p d x r ? ja ) eqn. 1 where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambie nt thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) eqn. 2 therefore, solving equations 1 and 2: k = p d x (t a + 273 c) + r ? ja x p d 2 eqn. 3 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 4.7 i/o pad electrical characteristics 4.7.1 i/o pad types the device provides four main i/o pad types depe nding on the associated alternate functions: ? slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?these pads provide transition fast enough for the serial communicati on channels with controlled current to reduce elect romagnetic emission. ? fast pads?these pads provide maximum speed. there are used for improved nexus debugging capability. ? input only pads?these pads are associated to adc channels and the external 32 khz crystal oscillator (sxosc) providing low input leakage. medium and fast pads can use slow configuration to reduce elect romagnetic emission, at the cost of reducing ac performance. electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 41 4.7.2 i/o input dc characteristics table 11 provides input dc electrical characteristics as described in figure 7 . figure 7. i/o input dc electrical characteristics definition table 11. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 ? na pt a = 25 c ? 2 ? dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi 2 2 in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. sr p wakeup input filtered pulse ? ? ? 40 ns w nfi 2 sr p wakeup input not filtered pulse ? 1000 ? ? ns v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 42 4.7.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 12 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 13 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 14 provides output driver char acteristics for i/o pads when in medium configuration. ? table 15 provides output driver char acteristics for i/o pads wh en in fast configuration. table 12. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a cpad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient co nfiguration during power- up. all pads but reset and nexus output (mdox, evto, mcko) are config ured in input or in high impedance state. 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd | cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 table 13. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ??v ci oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient c onfiguration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ??0.1v dd v ci ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ??0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 43 table 14. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ??v pi oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? ci oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? ci oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v ol cc c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.2v dd v pi ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd ci ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 ci ol = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd table 15. fast configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc p output high level fast configuration push pull i oh = ? 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ??v ci oh = ? 7ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? ci oh = ? 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 44 4.7.4 output pin transition times v ol cc p output low level fast configuration push pull i ol = 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v ci ol = 7ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd ci ol = 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are c onfigured in input or in high impedance state. table 16. output pin transition times symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max t tr cc d output transition time output pin 2 slow configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 ? ? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 ??50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 t tr cc d output transition time output pin 2 medium configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 siul.pcrx.src = 1 ? ? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin 2 fast configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 ?? 4ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 table 15. fast configuration output buffer electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 45 4.7.5 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 17 . table 18 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment should remain below the i dynseg maximum value. 2 c l includes device and package capacitances (c pkg < 5 pf). table 17. i/o supply segment package supply segment 123456 208 mapbga 1 1 208 mapbga available only as de velopment package for nexus2+ equivalent to 144 lqfp segment pad distribution mcko mdon/mseo 144 lqfp pin20?pin49 pin51?pin99 pin100?pin122 pin 123?pin19 ? ? 100 lqfp pin16?pin35 pin37?pin69 pin70?pin83 pin 84?pin15 ? ? 64 lqfp 2 2 all 64 lqfpinformation is indicative and must be confirmed during silicon validation. pin8?pin26 pin28?pin55 pin56?pin7 ? ? ? table 18. i/o consumption symbol c parameter conditions 1 value unit min typ max i swtslw ,2 cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed 2 cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst 2 cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 46 table 19 provides the weight of concurrent switching i/os. in order to ensure device functionality, the sum of the weight of concurrent switching i/os on a single segment should remain below the 100%. i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 19. i/o weight 1 pad 144/100 lqfp 64 lqfp 2 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 pb[3] 10% ? 12% ? 10% ? 12% ? pc[9] 10% ? 12% ? 10% ? 12% ? pc[14] 9% ? 11% ? 9% ? 11% ? pc[15] 9% 13% 11% 12% 9% 13% 11% 12% table 18. i/o consumption (continued) symbol c parameter conditions 1 value unit min typ max electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 47 pg[5] 9% ? 11% ? 9% ? 11% ? pg[4] 9% 12% 10% 11% 9% 12% 10% 11% pg[3] 9% ? 10% ? 9% ? 10% ? pg[2] 8% 12% 10% 10% 8% 12% 10% 10% pa[2]8%? 9% ? 8%? 9% ? pe[0] 8% ? 9% ? 8% ? 9% ? pa[1]7%? 9% ? 7%? 9% ? pe[1] 7% 10% 8% 9% 7% 10% 8% 9% pe[8] 7% 9% 8% 8% 7% 9% 8% 8% pe[9] 6% ? 7% ? 6% ? 7% ? pe[10] 6% ? 7% ? 6% ? 7% ? pa[0]5%8%6% 7%5%8%6% 7% pe[11] 5% ? 6% ? 5% ? 6% ? pg[9] 9% ? 10% ? 9% ? 10% ? pg[8] 9% ? 11% ? 9% ? 11% ? pc[11] 9% ? 11% ? 9% ? 11% ? pc[10] 9% 13% 11% 12% 9% 13% 11% 12% pg[7] 10% 14% 11% 12% 10% 14% 11% 12% pg[6] 10% 14% 12% 12% 10% 14% 12% 12% pb[0] 10% 14% 12% 12% 10% 14% 12% 12% pb[1] 10% ? 12% ? 10% ? 12% ? pf[9] 10% ? 12% ? 10% ? 12% ? pf[8] 10% 15% 12% 13% 10% 15% 12% 13% pf[12] 10% 15% 12% 13% 10% 15% 12% 13% pc[6] 10% ? 12% ? 10% ? 12% ? pc[7] 10% ? 12% ? 10% ? 12% ? pf[10] 10% 14% 12% 12% 10% 14% 12% 12% pf[11] 10% ? 11% ? 10% ? 11% ? pa[15] 9% 12% 10% 11% 9% 12% 10% 11% pf[13] 8% ? 10% ? 8% ? 10% ? pa[14] 8% 11% 9% 10% 8% 11% 9% 10% pa[4]8%? 9% ? 8%? 9% ? pa[13] 7% 10% 9% 9% 7% 10% 9% 9% table 19. i/o weight 1 pad 144/100 lqfp 64 lqfp 2 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 48 pa[12] 7% ? 8% ? 7% ? 8% ? pb[9] 1% ? 1% ? 1% ? 1% ? pb[8] 1% ? 1% ? 1% ? 1% ? pb[10] 6% ? 7% ? 6% ? 7% ? pf[0]6%? 7% ? 6%? 7% ? pf[1]7%? 8% ? 7%? 8% ? pf[2]7%? 8% ? 7%? 8% ? pf[3]7%? 9% ? 8%? 9% ? pf[4]8%? 9% ? 8%? 9% ? pf[5] 8% ? 10% ? 8% ? 10% ? pf[6] 8% ? 10% ? 9% ? 10% ? pf[7] 9% ? 10% ? 9% ? 11% ? pd[0]1%? 1% ? 1%? 1% ? pd[1]1%? 1% ? 1%? 1% ? pd[2]1%? 1% ? 1%? 1% ? pd[3]1%? 1% ? 1%? 1% ? pd[4]1%? 1% ? 1%? 1% ? pd[5]1%? 1% ? 1%? 1% ? pd[6]1%? 1% ? 1%? 1% ? pd[7]1%? 1% ? 1%? 1% ? pd[8]1%? 1% ? 1%? 1% ? pb[4] 1% ? 1% ? 1% ? 1% ? pb[5] 1% ? 1% ? 1% ? 2% ? pb[6] 1% ? 1% ? 1% ? 2% ? pb[7] 1% ? 1% ? 1% ? 2% ? pd[9]1%? 1% ? 1%? 2% ? pd[10] 1% ? 1% ? 1% ? 2% ? pd[11] 1% ? 1% ? 1% ? 2% ? pb[11] 11% ? 13% ? 17% ? 21% ? pd[12] 11% ? 13% ? 18% ? 21% ? pb[12] 11% ? 13% ? 18% ? 21% ? pd[13] 10% ? 12% ? 18% ? 21% ? pb[13] 10% ? 12% ? 18% ? 21% ? table 19. i/o weight 1 pad 144/100 lqfp 64 lqfp 2 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 49 pd[14] 10% ? 12% ? 18% ? 21% ? pb[14] 10% ? 12% ? 18% ? 21% ? pd[15] 10% ? 11% ? 18% ? 21% ? pb[15] 9% ? 11% ? 18% ? 21% ? pa[3] 9% ? 11% ? 18% ? 21% ? pg[13] 9% 13% 10% 11% 18% 26% 21% 23% pg[12] 9% 12% 10% 11% 18% 26% 21% 23% ph[0] 5% 8% 6% 7% 18% 26% 21% 23% ph[1] 5% 7% 6% 6% 18% 26% 21% 23% ph[2] 5% 6% 5% 6% 18% 25% 21% 22% ph[3] 4% 6% 5% 5% 18% 25% 21% 22% pg[1] 4% ? 4% ? 18% ? 21% ? pg[0] 3% 4% 4% 4% 17% 25% 21% 22% pf[15] 3% ? 4% ? 17% ? 20% ? pf[14] 4% 5% 5% 5% 16% 23% 20% 21% pe[13] 4% ? 5% ? 16% ? 19% ? pa[7] 5% ? 6% ? 16% ? 19% ? pa[8] 5% ? 6% ? 16% ? 19% ? pa[9] 5% ? 6% ? 15% ? 18% ? pa[10] 6% ? 7% ? 15% ? 18% ? pa[11] 6% ? 8% ? 14% ? 17% ? pe[12] 7% ? 8% ? 11% ? 14% ? pg[14] 7% ? 8% ? 10% ? 12% ? pg[15] 7% 10% 8% 9% 10% 14% 12% 12% pe[14] 7% ? 8% ? 9% ? 11% ? pe[15] 7% 9% 8% 8% 9% 12% 10% 11% pg[10] 6% ? 8% ? 8% ? 10% ? pg[11] 6% 9% 7% 8% 8% 11% 9% 10% pc[3]6%? 7% ? 7%? 9% ? pc[2]6%8%7% 7%6%9%8% 8% pa[5]5%7%6% 6%6%8%7% 7% pa[6]5%? 6% ? 5%? 6% ? pc[1]5%? 5% ? 5%? 5% ? table 19. i/o weight 1 pad 144/100 lqfp 64 lqfp 2 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 50 pc[0]6%9%7% 8%6%9%7% 8% pe[2] 7% 10% 9% 9% 7% 10% 9% 9% pe[3] 8% 11% 9% 9% 8% 11% 9% 9% pc[5] 8% 11% 9% 10% 8% 11% 9% 10% pc[4] 8% 12% 10% 10% 8% 12% 10% 10% pe[4] 8% 12% 10% 11% 8% 12% 10% 11% pe[5] 9% 12% 10% 11% 9% 12% 10% 11% ph[4] 9% 13% 11% 11% 9% 13% 11% 11% ph[5] 9% ? 11% ? 9% ? 11% ? ph[6] 9% 13% 11% 12% 9% 13% 11% 12% ph[7] 9% 13% 11% 12% 9% 13% 11% 12% ph[8] 10% 14% 11% 12% 10% 14% 11% 12% pe[6] 10% 14% 12% 12% 10% 14% 12% 12% pe[7] 10% 14% 12% 12% 10% 14% 12% 12% pc[12] 10% 14% 12% 13% 10% 14% 12% 13% pc[13] 10% ? 12% ? 10% ? 12% ? pc[8] 10% ? 12% ? 10% ? 12% ? pb[2] 10% 15% 12% 13% 10% 15% 12% 13% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2 all 64 lqfpinformation is indicative and mu st be confirmed during silicon validation. table 19. i/o weight 1 pad 144/100 lqfp 64 lqfp 2 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 weight 5v sre=0 weight 5v sre=1 weight 3.3v sre=0 weight 3.3v sre=1 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 51 4.8 reset electrical characteristics the device implements a dedicat ed bidirectional reset pin. figure 8. start-up reset requirements figure 9. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 52 table 20. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v c push pull, i ol = 1ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 this transient configuration does not occurs when device is used in the v dd = 3.3 v 10% range. ? ? 0.1v dd c push pull, i ol = 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin 3 3 c l includes device and package capacitance (c pkg <5pf). c l = 25pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 10 ns c l = 50pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a pv dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 cv dd = 5.0 v 10%, pad3v5v = 1 2 10 ? 250 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 53 4.9 power management electrical characteristics 4.9.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: ? hv?high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. ? bv?high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . ? lv?low voltage internal power supply for core, fmpll and fl ash digital logic. this is generated by the internal voltage regulator but provided outside to connect stability capacito r. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor?low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla?low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla?low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll?low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 10. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. ca pacitances should be placed on the board as near as possible to the associated pins . care should also be taken to limit the seri al inductance of the board to less than 5 nh. c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 (lv_cor/lv_pll) c dec2 (supply/io decoupling) device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn gnd gnd gnd gnd MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 54 each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 4.5, ?recommen ded operating conditions ). table 21. voltage regulator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max c regn sr ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg sr ? stability capacitor equivalent serial resistance ???0.2 ? c dec1 sr ? decoupling capacitance 2 ballast 2 this capacitance value is driven by the constraint s of the external voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. v dd_bv /v ss_lv pair: v dd_bv = 4.5v to 5.5v 100 3 3 this value is acceptable to guar antee operation from 4.5 v to 5.5 v 470 4 ?nf v dd_bv /v ss_lv pair: v dd_bv = 3 v to 3.6 v 400 ? c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf v mreg cc t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming 1.15 1.28 1.32 i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low power regulator output voltage after trimming 1.15 1.23 1.32 v i lpreg sr ? low power regulator current provided to v dd_lv domain ? ?? 15 ma i lpregint cc d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 a ? i lpreg = 0 ma; t a = 55 c ? 5? v ulpreg cc p ultra low power regulator output voltage after trimming 1.15 1.23 1.32 v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c ?? 100 a i ulpreg = 0 ma; t a = 55 c ? 2? i dd_bv cc d in-rush current on v dd_bv during power-up 5 ?? ? 400 6 ma electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 55 4.9.2 voltage monitor electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initia lization, as well as four low voltage detectors (lvds) to monitor the v dd and the v dd_lv voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 note when enabled, power domain no. 2 is monitored through lvd_digbkp. figure 11. low voltage monitor vs reset 4 external regulator and capacitance circuitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 5 in-rush current is seen only for short time during power-up and on standby exit (max 20 s, depending on external lv capacitances to be load) 6 the duration of the in-rush current depends on the capac itance placed on lv pins. bv decaps must be sized accordingly. refer to imreg value for minimum amount of current to be provided in cc. v dd v lvdhvxh reset v lvdhvxl MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 56 4.10 low voltage domain power consumption table 23 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 22. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v porup sr p supply for functional por module ? 1.0 ? 5.5 v v porh cc p power-on reset threshold t a = 25 c, after trimming 1.5 ? 2.6 t ? 1.5 ? 2.6 v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold ? ? ? 2.95 v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold 2.6 ? 2.9 v lv d h v 5 h cc t lvdhv5 low voltage detector high threshold ? ? 4.5 v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold 3.8 ? 4.4 v lvd lv c o r l cc p lvdlvcor low voltage detector low threshold 1.08 ? 1.15 v lvdlvbkpl cc p lvdlvbkp low voltage detector low threshold 1.08 ? 1.14 table 23. low voltage power domain electrical characteristics symbol c parameter conditions 1 value unit min typ max i ddmax 2 cc d run mode maximum average current ??115140 3 ma i ddrun 4 cc t run mode typical average current 5 f cpu = 8 mhz ? 7 ? ma tf cpu = 16 mhz ? 18 ? tf cpu = 32 mhz ? 29 ? pf cpu = 48 mhz ? 40 ? pf cpu = 64 mhz ? 51 ? i ddhalt cc c halt mode current 6 slow internal rc oscillator (128 khz) running t a =25c ? 8 15 ma pt a = 125 c ? 14 25 i ddstop cc p stop mode current 7 slow internal rc oscillator (128 khz) running t a =25c ? 180 700 8 a dt a =55c ? 500 ? dt a =85c ? 1 ? ma dt a = 105 c ? 2 ? pt a = 125 c ? 4.5 12 8 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 57 i ddstdby2 cc p standby2 mode current 9 slow internal rc oscillator (128 khz) running t a = 25 c ? 30 100 a dt a =55c ? 75 ? dt a =85c ? 180 ? dt a = 105 c ? 315 ? pt a = 125 c ? 560 1700 i ddstdby1 cc t standby1 mode current 10 slow internal rc oscillator (128 khz) running t a = 25 c ? 20 60 a dt a =55c ? 45 ? dt a =85c ? 100 ? dt a = 105 c ? 165 ? dt a = 125 c ? 280 900 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 running consumption is given on voltage regulator supply (v ddreg ). i ddmax is composed of three components: i ddmax = i dd (vdd_bv) + i dd (vdd_hv) + i dd (vdd_hv_adc). it does not include a fourth component linked to i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value with all peripherals running, and code fetched from code flash whil e modify operation on-going on data flash. it is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. 3 higher current may be sinked by device during power-up and standby exit. please refer to in rush current on ta bl e 2 1 . 4 run current measured with typical applic ation with accesses on both flash and ram. 5 only for the ?p? classification: data and code flash in no rmal power. code fetched from ram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) periph erals on (emios/ctu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. 6 data flash power down. code flash in low power. rc-osc128khz & rc-osc 16mhz on. 10mhz xtal clock. flexcan: instances: 0, 1, 2 on (clock ed but not reception or transmission), inst ances: 4, 5, 6 cl ock gated. linflex: instances: 0, 1, 2 on (clocked but not reception or tran smission), instance: 3 clock gated. emios: instance: 0 on (16 channels on pa[0]-pa[11] and pc[12]-pc[15]) with pwm 20khz, instance: 1 clock gated. dspi: instance: 0 (clocked but no communication). rtc/api on.pit on. st m on. adc on but not conversion except 2 analogue watchdog 7 only for the ?p? classification: no cl ock, rc 16mhz off, rc128khz on, pll of f, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 8 when going from run to stop mode and the core consumpti on is > 6 ma , it is normal operation for the main regulator module to be kept on by the on-chip current moni toring circuit. this is most likely to occur with junction temperatures exceeding 125 c and under these circumstances, it is possible for the current to initially exceed the maximum stop specification by up to 2 ma. after enteri ng stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatica lly switched off when the load current is below 6 ma. 9 only for the ?p? classification: ulpreg on, hp/lpvreg off, 32kb ram on, device configured for minimum consumption, all possible modules switched-off. 10 ulpreg on, hp/lpvreg off, 8kb ram on, device conf igured for minimum consumption, all possible modules switched-off. table 23. low voltage power domain electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 58 4.11 flash memory electrical characteristics 4.11.1 program/erase characteristics table 24 shows the program and erase characteristics. table 24. program and erase specifications symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?2250500s t 16kpperase 16 kb block pre-program and erase time ? 300 500 5000 ms t 32kpperase 32 kb block pre-program and erase time ? 400 600 5000 ms t 128kpperase 128 kb block pre-program and erase time ? 800 1300 7500 ms t esus cc d erase suspend latency ? ? 30 30 s table 25. flash module life symbol c parameter conditions value unit min typ max p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100,000 ? ? cycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10,000 100,000 ? cycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1,000 100,000 ? cycles retention cc c minimum data retention at 85 c average ambient temperature 1 blocks with 0?1,000 p/e cycles 20 ? ? years blocks with 1,001?10,000 p/e cycles 10 ? ? years blocks with 10,001?100,000 p/e cycles 5??years electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 59 1 ambient temperature averaged over duration of applic ation, not to exceed re commended product operating temperature range. ecc circuitry provides correction of single bit faults and is used to improve further automotive reliability results. some units will experience single bit corrections throughout the life of the product with no impact to product reliability. table 26. flash read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified max unit f read cc p maximum frequency for flas h reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 60 4.11.2 flash power supply dc characteristics table 27 shows the power supply dc char acteristics on external supply. table 27. code flash power supply dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max i fread 2 2 this value is only relative to the actual duration of the read cycle cc d sum of the current consumption on v ddhv and v ddbv on read access code flash module read f cpu = 64 mhz 3 3 f cpu 64 mhz can be achieved only at up to 105 c ?1533ma data flash module read f cpu = 64 mhz 3 ?1533 i fmod 2 cc d sum of the current consumption on v ddhv and v ddbv on matrix modification (program/erase) program/erase on-going while reading code flash registers f cpu = 64 mhz 3 ?1533ma program/erase on-going while reading data flash registers f cpu = 64 mhz 3 ?1533 i flpw cc d sum of the current consumption on v ddhv and v ddbv during code flash low-power mode ??900a during data flash low-power mode ??900 i fpwd cc d sum of the current consumption on v ddhv and v ddbv during code flash power-down mode ??150a during data flash power-down mode ??150 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 61 4.11.3 start-up/switch-off timings table 28. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max t flarstexit cc t delay for flash module to exit reset mode code flash ? ? 125 s t data flash ? ? 125 t flalpexit cc t delay for flash module to exit low-power mode code flash ? ? 0.5 t data flash ? ? 0.5 t flapdexit cc t delay for flash module to exit power-down mode code flash ? ? 30 t data flash ? ? 30 t flalpentry cc t delay for flash module to enter low-power mode code flash ? ? 0.5 t data flash ? ? 0.5 t flapdentry cc t delay for flash module to enter power-down mode code flash ? ? 1.5 t data flash ? ? 1.5 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 62 4.12 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sample basis during produ ct characterization. 4.12.1 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for his application. ? software recommendations: ? the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials: ? most of the common failures (unexpected rese t and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. 4.12.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec 61967-1 standard, which specifies the general conditions for emi measurements. 4.12.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. table 29. emi radiated emission measurement 1,2 1 emi testing and i/o port waveforms per iec 61967-1, -2, -4 2 for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 ? 1000 mhz f cpu sr ? operating frequency ? ? 64 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, lqfp144 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 64 mhz no pll frequency modulation ? ? 18 dbv 2% pll frequency modulation ? ? 14 dbv electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 63 4.12.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size de pends on the number of suppl y pins in the device (3 pa rts*(n+1) suppl y pin). this test conforms to the aec- q100-002/-003/-011 standard. 4.12.3.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 30. esd absolute maximum ratings 1 2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol c ratings conditions class max value unit v esd(hbm) cc t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) cc t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) cc t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) table 31. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 125 c conforming to jesd 78 ii level a MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 64 4.13 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 12 describes a simple model of the internal oscillat or driver and provides an example of a connection for an oscillator or a resonator. table 32 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. figure 12. crystal oscillator and resonator connection scheme c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd note: xtal/extal must not be directly used to drive external circuits. electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 65 figure 13. fast external crystal oscillator (4 to 16 mhz) electrical characteristics table 32. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. shunt capacitance between xtalout and xtalin c0 2 (pf) 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 66 table 33. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max f fxosc sr ? fast external crystal oscillator frequency ? 4.0 ? 16.0 mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc p oscillation operating point ? ? 0.95 v i fxosc ,2 2 stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) cc t fast external crystal oscillator consumption ??23 m a t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 67 4.14 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. figure 14. crystal oscillator and resonator connection scheme figure 15. equivalent circuit of a quartz crystal osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal resonator device note: osc32k_xtal/osc32k_extal must not be directly used to drive external circuits. c0 c2 c1 c2 r m c1 l m c m crystal MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 68 figure 16. slow external crystal oscillator (32 khz) electrical characteristics table 34. crystal motional characteristics 1 1 the crystal used is epson toyocom mc306. symbol parameter conditions value unit min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground 2 2 this is the recommended range of load capacitance at osc32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. ?1 8?2 8 p f r m 3 3 maximum esr (r m ) of the crystal is 50 k ? motional resistance ac coupled @ c0 = 2.85 pf 4 4 c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins ??65k ? ac coupled @ c0 = 4.9 pf 4 ??50 ac coupled @ c0 = 7.0 pf 4 ??35 ac coupled @ c0 = 9.0 pf 4 ??30 oscon bit (osc_ctl register) t sxoscsu 1 v osc32k_xtal v sxosc valid internal clock 90% 10% 1/f sxosc 0 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 69 4.15 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. table 35. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max f sxosc sr ? slow external crystal oscillator frequency ? 32 32.768 40 khz v sxosc cc t oscillation amplitude ? ? 2.1 ? v i sxoscbias cc t oscillation bias current ? ? 2.5 ? a i sxosc cc t slow external crystal oscillator consumption ???8a t sxoscsu cc t slow external crystal oscillator start-up time ???2 2 2 start-up time has been me asured with epson toyocom mc306 crystal. variation ma y be seen with other crystal s table 36. fmpll electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max f pllin sr ? fmpll reference clock 2 2 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ?4?64mhz ? pllin sr ? fmpll reference clock duty cycle 2 ?4 0 ? 6 0 % f pllout cc d fmpll output clock frequency ? 16 ? 64 mhz f vco 3 3 frequency modulation is considered 4% cc p vco frequency without frequency modulation ? 256 ? 512 mhz c vco frequency with frequency modulation ? 245 ? 533 f cpu sr ? system clock frequency ? ? ? 64 mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s ? t ltjit cc ? fmpll long term jitter f pllin = 16 mhz (resonator) , f pllclk @ 64 mhz, 4000 cycles ? ? 10 ns i pll cc c fmpll consumption t a = 25 c ? ? 4 ma MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 70 4.16 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator. this is used as the default clock at the power-up of the device. 4.17 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator. this can be used as the reference clock for the rtc module. table 37. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun 2, 2 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 125 c ? ? 10 a i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu cc c fast internal rc oscillator start-up time v dd = 5.0 v 10% ? 1.1 2.0 s ? fircpre cc t fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1?+1% ? firctrim cc t fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc p fast internal rc oscillator variation in overtemperature and supply with respect to f firc at t a = 25 c in high-frequency configuration ? ? 5?+5% electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 71 table 38. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc 2, 2 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2?+2% ? sirctrim cc c slow internal rc oscillator trimming step ?? 2 . 7 ? ? sircvar cc c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? +10 % MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 72 4.18 adc electrical characteristics 4.18.1 introduction the device provides a 10-bit successive approxima tion register (sar) analog-to-digital converter. figure 17. adc characteristic and error definitions 4.18.2 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 73 possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c *c s ), where f c represents the conversion rate at the considered channel). to minimize the error indu ced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 74 equation 4 generates a constraint for external network design, in pa rticular on a resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 18. input equivalent circui t (precise channels) figure 19. input equivalent circuit (extended channels) r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 75 a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit in figure 18 ): a charge sharing phenomenon is installed when the sampling phase is st arted (a/d switch close). figure 20. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 2. a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 76 eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 21. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : ? 2 r l ? c s c p1 c p2 ++ ?? ? 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ?? =t s ? v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 77 eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 4.18.3 adc electrical characteristics table 39. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ? 1 ? na ct a = 25 c ? 1 ? ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 40. adc conversion characteristics symbol c parameter conditions 1 value unit min typ max v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) 2 ? ? 0.1 ? 0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd +0.1 v v ainx sr ? analog input voltage 3 ?v ss_adc ? 0.1 ? v dd_adc +0.1 v f adc sr ? adc analog frequency ? 6? 32 + 4% mhz ? adc_sys sr ? adc digital clock duty cycle (ipg_clk) adclksel = 1 4 45 ? 55 % i adcpwd sr ? adc0 consumption in power down mode ??? 50 a i adcrun sr ? adc0 consumption in running mode ??? 4 ma t adc_pu sr ? adc power up delay ? ?? 1.5 s v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ?? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 78 t adc_s cc t sample time 5 f adc = 32 mhz, inpsamp = 17 0.5 ? s f adc = 6 mhz, inpsamp = 255 ??42 t adc_c cc p conversion time 6 f adc = 32 mhz, inpcmp = 2 0.625 ? s c s cc d adc input sampling capacitance ??? 3 pf c p1 cc d adc input pin capacitance 1 ??? 3 pf c p2 cc d adc input pin capacitance 2 ?? ? 1 pf c p3 cc d adc input pin capacitance 3 ??? 1 pf r sw1 cc d internal resistance of analog source ??? 3 k? r sw2 cc d internal resistance of analog source ? ? ? 2 k? r ad cc d internal resistance of analog source ??? 2 k? i inj sr ? input current injection current injection on one adc input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5 ? 5 | inl | cc t absolute value for integral non-linearity no overload ? 0.5 1.5 lsb | dnl | cc t absolute differential non-linearity no overload ? 0.5 1.0 lsb | ofs | cc t absolute offset error ? ? 0.5 ? lsb | gne | cc t absolute gain error ?? 0.6 ? lsb tuep cc p total unadjusted error 7 for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 3 tuex cc t total unadjusted error 7 for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ss_adc and v dd_adc limits, remaining on absolute maximu m ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. table 40. adc conversion characteristics (continued) symbol c parameter conditions 1 value unit min typ max electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 79 4.19 on-chip peripherals 4.19.1 current consumption 4 duty cycle is ensured by using system clock without prescaling. when adclksel = 0, th e duty cycle is ensured by internal divider by 2. 5 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 6 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7 total unadjusted error: the maximum error that occurs wit hout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 41. on-chip peripherals current consumption 1 symbol c parameter conditions value unit typ i dd_bv(can) cc t can (flexcan) supply current on v dd_bv 500 kbps total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal@ 8mhz used as can engine clock source ? message sending period is 580 s 8 * f periph + 85 a 125 kbps 8 * f periph + 27 i dd_bv(emios) cc t emios supply current on v dd_bv static consumption: ? emios channel off ? global prescaler enabled 29 * f periph dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3 i dd_bv(sci) cc t sci (linflex) supply current on v dd_bv total (static + dynamic) consumption: ? lin mode ? baudrate: 20 kbps 5 * f periph + 31 i dd_bv(spi) cc t spi (dspi) supply current on v dd_bv ballast static consumption (only clocked) 1 ballast dynamic consumption (contin u ous communication): ? baudrate: 2 mbit ? trasmission every 8 s ? frame: 16 bits 16 * f periph MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 80 i dd_bv(adc) cc t adc supply current on v dd_bv v dd = 5.5 v ballast static consumption (no conversion) 41 * f periph a v dd = 5.5 v ballast dynamic consumption (contin u ous conversion) 5 * f periph i dd_hv_adc(adc) cc t adc supply current on v dd_hv_adc v dd = 5.5 v analog static consumption (no conversion) 2 * f periph v dd = 5.5 v analog dynamic consumption (contin u ous conversion) 75 * f periph + 32 i dd_hv(flash) cc t cflash + dflash supply current on v dd_hv_adc v dd = 5.5 v ? 8.21 ma i dd_hv(pll) cc t pll supply current on v dd_hv v dd = 5.5 v ? 3 * f periph a 1 operating conditions: t a = 25 c, f periph = 8 mhz to 64 mhz table 41. on-chip peripherals current consumption 1 (continued) symbol c parameter conditions value unit typ MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 81 4.19.2 dspi characteristics table 42. dspi characteristics 1 no. symbol c parameter dspi0/dspi1 dspi2 unit min typ max min typ max 1t sck sr d sck cycle time master mode (mtfe = 0) 125 ? ? 333 ? ? ns ds l a v e m o d e (mtfe = 0) 125 ? ? 333 ? ? d master mode (mtfe = 1) 83 ? ? 125 ? ? ds l a v e m o d e (mtfe = 1) 83 ? ? 125 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu ?? f cpu mhz ? ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1->0 master mode ? ? 130 2 ?? 15 3 ns ? ? t asc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1->1 master mode ? ? 130 3 ? ? 130 3 ns 2t cscext 4 sr d cs to sck delay slave mode 32 ? ? 32 ? ? ns 3t ascext 5 sr d after sck delay slave mode 1/f dspi + 5 ? ? 1/f dspi + 5 ? ? ns 4t sdc cc d sck duty cycle master mode ? t sck /2 ? ? t sck /2 ? ns sr d slave mode t sck /2 ? ? t sck /2 ? ? 5t a sr d slave access time slave mode ? ? 1/f dspi + 70 ? ? 1/f dspi + 130 ns 6t di sr d slave sout disable time slave mode 7 ? ? 7 ? ? ns 9t sui sr d data setup time for inpu ts master mode 43 ? ? 145 ? ? ns slave mode 5 ? ? 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? 0 ? ? ns slave mode 2 6 ?? 2 6 ?? MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 82 11 t suo 7 cc d data valid after sck edge master mode ? ? 32 ? ? 50 ns slave mode ? ? 52 ? ? 160 12 t ho 7 cc d data hold time for outputs master mode 0 ? ? 0 ? ? ns slave mode 8 ? ? 13 ? ? 1 operating conditions: c out = 10 to 50 pf, slew in = 3.5 to 15 ns. 2 maximum value is reached when csn pad is configured as slow pad while sck pad is configured as medium. a positive value means t hat sck starts before csn is asserted. dspi2 has only slow sck available. 3 maximum value is reached when csn pad is c onfigured as medium pad while sck pad is conf igured as slow. a positive value means t hat csn is deasserted before sck. dspi0 and dspi1 have only medium sck available. 4 the t csc delay value is configurable through a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t csc to ensure positive t cscext . 5 the t asc delay value is configurable through a register. when configuring t asc (using pasc and asc fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t asc to ensure positive t ascext . 6 this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr register. 7 sck and sout configured as medium pad table 42. dspi characteristics 1 (continued) no. symbol c parameter dspi0/dspi1 dspi2 unit min typ max min typ max electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 83 figure 22. dspi classic spi timing ? master, cpha = 0 figure 23. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta bl e 4 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 2 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 84 figure 24. dspi classic spi timing ? slave, cpha = 0 figure 25. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 2 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 2 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 85 figure 26. dspi modified transfer format timing ? master, cpha = 0 figure 27. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 2 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 2 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 86 figure 28. dspi modified transfer format timing ? slave, cpha = 0 figure 29. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta bl e 4 2 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta b l e 4 2 electrical characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 87 4.19.3 nexus characteristics figure 30. nexus tdi, tms, tdo timing table 43. nexus characteristics no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 64 ? ? ns 2t mcyc cc d mcko cycle time 32 ? ? ns 3t mdov cc d mcko low to mdo data valid ? ? 8 ns 4t mseov cc d mcko low to mseo_b data valid ? ? 8 ns 5t evtov cc d mcko low to evto data valid ? ? 8 ns 10 t ntdis cc d tdi data setup time 15 ? ? ns t ntmss cc d tms data setup time 15 ? ? ns 11 t ntdih cc d tdi data hold time 5 ? ? ns t ntmsh cc d tms data hold time 5 ? ? ns 12 t tdov cc d tck low to tdo data valid 35 ? ? ns 13 t tdoi cc d tck low to tdo data invalid 6 ? ? ns 10 tck tms, tdi tdo 11 12 note: numbers shown reference ta bl e 4 3 MPC5604B/c microcontrolle r data sheet, rev. 8 electrical characteristics freescale semiconductor 88 4.19.4 jtag characteristics figure 31. timing diagram ? jtag boundary scan table 44. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 33 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 4 4 3/5 2/4 7 6 package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 89 5 package characteristics 5.1 package mechanical data 5.1.1 64 lqfp MPC5604B/c microcontrolle r data sheet, rev. 8 package characteristics freescale semiconductor 90 figure 32. 64 lqfp package mechanical drawing (1 of 3) package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 91 figure 33. 64 lqfp package mechanical drawing (2 of 3) MPC5604B/c microcontrolle r data sheet, rev. 8 package characteristics freescale semiconductor 92 figure 34. 64 lqfp package mechanical drawing (3 of 3) package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 93 5.1.2 100 lqfp figure 35. 100 lqfp package mechanical drawing (1 of 3) MPC5604B/c microcontrolle r data sheet, rev. 8 package characteristics freescale semiconductor 94 figure 36. 100 lqfp package mechanical drawing (2 of 3) package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 95 figure 37. 100 lqfp package mechanical drawing (3 of 3) MPC5604B/c microcontrolle r data sheet, rev. 8 package characteristics freescale semiconductor 96 5.1.3 144 lqfp figure 38. 144 lqfp package mechanical drawing (1 of 2) package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 97 figure 39. 144 lqfp package mechanical drawing (2 of 2) MPC5604B/c microcontrolle r data sheet, rev. 8 package characteristics freescale semiconductor 98 5.1.4 208 mapbga figure 40. 208 mapbga package mechanical drawing (1 of 2) package characteristics MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 99 figure 41. 208 mapbga package mechanical drawing (2 of 2) MPC5604B/c microcontrolle r data sheet, rev. 8 ordering information freescale semiconductor 100 6 ordering information figure 42. commercial product code structure 1 208 mapbga available only as de velopment package for nexus2+ 7 document revision history table 45 summarizes revisions to this document. table 45. revision history revision date description of changes 1 04-apr-2008 initial release. qualification status powerpc core automotive platform core version flash size (core dependent) product temperature spec. mpc56 b mll4 example code: 04 package code frequency qualification status m = mc status s = auto qualified p = pc status automotive platform 56 = ppc in 90nm core version 0 = e200z0 flash size (z0 core) 2 = 256 kb 3 = 384 kb 4 = 512 kb product b = body c = gateway fab and mask indicator f = atmc 1 = maskset revision r = tape & reel (blank if tray) r temperature spec. c = -40 to 85 c v = -40 to 105 c m = -40 to 125 c package code lh = 64 lqfp ll = 100 lqfp lq = 144 lqfp mg = 208 mapbga 1 frequency 4 = up to 48 mhz 6 = up to 64 mhz fab and mask indicator f1 document revision history MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 101 2 06-mar-2009 made minor editing and formatting changes to improve readability harmonized oscillator naming throughout document features: ?replaced 32 kb with 48 kb as max sram size ?updated descripiton of intc ?changed max number of gpio pins from 121 to 123 updated section 1.2, description updated ta b l e 2 added section 2, block diagram section 3, package pinouts and signal descriptions : removed signal descriptions (these are found in the device reference manual) updated figure 5 : ?replaced vpp with vss_hv on pin 18 ?added ma[1] as af3 for pc[10] (pin 28) ?added ma[0] as af2 for pc[3] (pin 116) ?changed description for pin 120 to ph[10] / gpio[122] / tms ?changed description for pin 127 to ph[9] / gpio[121] / tck ?replaced nmi[0] with nmi on pin 11 updated figure 4 : ?replaced vpp with vss_hv on pin 14 ?added ma[1] as af3 for pc[10] (pin 22) ?added ma[0] as af2 for pc[3] (pin 77) ?changed description for pin 81 to ph[10] / gpio[122] / tms ?changed description for pin 88 to ph[9] / gpio[121] / tck ?removed e1uc[19] from pin 76 ?replaced [11] with wkup[11] for pb[3] (pin 1) ?replaced nmi[0] with nmi on pin 7 updated figure 6 : ?changed description for ball b8 from tck to ph[9] ?changed description for ball b9 from tms to ph[10] ?updated descriptions for balls r9 and t9 added section 4.2, parameter classification and tagged parameters in tables where appropriate added section 4.3, nvusro register updated ta b l e 5 section 4.5, recommended operating conditions : added note on ram data retention to end of section updated ta b l e 6 and ta bl e 7 added section 4.6.1, package th ermal characteristics updated section 4.6.2, power considerations updated figure 7 updated ta b l e 9 , ta b l e 1 0 , ta b l e 1 1 , ta b l e 1 2 and ta b l e 1 3 added section 4.7.4, output pin transition times updated ta b l e 1 6 updated figure 8 updated ta b l e 1 8 section 4.9.1, voltage regulator electrical characteristics : amended description of lv _ p l l figure 10 : exchanged position of symbols c dec1 and c dec2 updated ta b l e 1 9 table 45. revision history (continued) revision date description of changes MPC5604B/c microcontrolle r data sheet, rev. 8 document revision history freescale semiconductor 102 2 06-mar-2009 added figure 11 updated ta b l e 2 0 and ta b l e 2 1 updated section 4.11, flash memory electrical characteristics added section 4.12, electromagnetic compatibility (emc) characteristics updated section 4.13, fast external crystal oscillator (4 to 16 mhz) electrical characteristics updated section 4.14, slow external crystal oscillat or (32 khz) electrical characteristics updated ta b l e 3 4 , ta b l e 3 5 and ta b l e 3 6 added section 4.19, on-chip peripherals added ta bl e 3 7 updated ta b l e 3 8 updated ta b l e 4 7 added section appendix a, abbreviations 4 06-aug-2009 updated figure 6 ta b l e 5 ?v dd_adc : changed min value for ?relative to v dd ? condition ?v in : changed min value for ?relative to v dd ? condition ?i corelv : added new row ta b l e 7 ?t a c-grade part, t j c-grade part, t a v-grade part, t j v-grade part, t a m-grade part, t j m-grade part : added new rows ? changed capacitance value in footnote ta b l e 1 4 ? medium configuration: added condition for pad3v5v = 0 updated figure 10 ta b l e 1 9 ?c dec1 : changed min value ?i mreg: changed max value ?i dd_bv : added max value footnote ta b l e 2 0 ?v lv d h v 3 h : changed max value ?v lv d h v 3 l : added max value ?v lv d h v 5 h : changed max value ?v lv d h v 5 l : added max value updated ta b l e 2 1 ta b l e 2 3 ? retention: deleted min value footno te for ?blocks with 100,000 p/e cycles? ta b l e 3 1 ?i fxosc : added typ value ta b l e 3 3 ?v sxosc : changed typ value ?t sxoscsu : added max value footnote ta b l e 3 4 ? ? t lt j i t : added max value updated figure 36 table 45. revision history (continued) revision date description of changes document revision history MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 103 5 02-nov-2009 in the ?MPC5604B/c series block summary? table, added a new row. in the ?absolute maximum ratings? table, changed max value of v dd_bv , v dd_adc , and v in . in the ?recommended operating conditions (3.3 v)? table, deleted min value of tv dd . in the ?reset electrical characterist ics? table, changed footnotes 3 and 5. in the ?voltage regulator electrical characteristics? table: ?c regn : changed max value. ?c dec1 : split into 2 rows. ? updated voltage values in footnote 4 in the ?low voltage monitor electrical characteristics? table: ? updated column conditions. ?v lv d lv c o r l , v lvdlvbkpl : changed min/max value. in the ?program and erase specificati ons? table, added initial max valueof t dwprogram . in the ?flash module life? table, changed min value for blocks with 100k p/e cycles in the ?flash power supply dc electrical characteristics? table: ?i fread , i fmod : added typ value. ? added footnote 1. added ? nvusro[watchdog_en] field description? section. section 4.18: ?adc electr ical characteristics? has been moved up in hierarchy (it was section 4.18.5). in the ? adc conversion characteristics? table, changed initial max value of r ad . in the ?on-chip peripherals current consumption? table: ? removed min/max from the heading. ? changed unit of measurement an d consequently rounded the values. table 45. revision history (continued) revision date description of changes MPC5604B/c microcontrolle r data sheet, rev. 8 document revision history freescale semiconductor 104 6 15-mar-2010 in the ?introduction ? section, relocated a note. in the ?MPC5604B/c device comparison? ta ble, added footnote regarding sci and can. in the ?absolute maximum ratings? table, removed the min value of v in relative tio v dd . in the ?recommended operating conditions (3.3 v)? table: ?t a c-grade part, t j c-grade part, t a v-grade part, t j v-grade part, t a m-grade part, t j m-grade part : added new rows. ?tv dd : made single row. in the ?lqfp thermal characteristics? table, added more rows. removed ?208 mapbga thermal characteristics? table. in the ?i/o consuption? table: ? removed i dynseg row. ? added ?i/o weight ? table. in the ?voltage regulator electrical characteristics? table: ? updated the values. ? removed i vregref and i vredlvd12 . ? added a note about i dd_bc . in the ?low voltage monitor electrical characteristics? table: ? updated v porh values. ? updated v lv d lv c o r l value. entirely updated the ?low voltage power domain electrical characteristics? table. in the ?program and erase specifications? table, inserted t eslat row. entirely updated the ?flash power supply dc electrical characteristics? table. entirely updated the ?start-up time/switch-off time? table. in the ?crystal oscillator and resonator connection scheme? figure, relocated a note. in the ?slow external crystal oscillator (32 khz) electrical characteristics? table: ? removed g msxosc row. ? inserted values of i sxoscbias . entirely updated the ?fast internal rc oscillator (16 mhz) electrical characteristics? table. in the ?adc conversion characteristics? table: updated the description of the conditions of t adc_pu and t adc_s. entirely updated the ?dspi characteristics? table. in the ?orderable part number summary? table, modified some orderable part number. updated the ?commercial prod uct code structure? figure. removed the note about the condition from ?flash read access timing? table removed the notes that assert the values need to be confirmed before validation exchanged the order of ?lqfp 100-pin confi guration? and ?lqfp 1 44-pin configuration? exchanged the order of ?lqfp 100-pin package mechanical drawing? and ?lqfp 144-pin package mechanical drawing? table 45. revision history (continued) revision date description of changes document revision history MPC5604B/c microcontroller data sheet, rev. 8 freescale semiconductor 105 7 05-jul-2010 added 64 lqfp package information updated the ?features? section. figures ?lqfp 100-pin configuration? a nd ?lqfp 100-pin configuration?: removed alternate function information added ?functional port pin descriptions? table added edma block in the ?MPC5604B/c series block diagram? figure deleted the ?nvusro[watchdog_en] field description? section in the ?recommended operating conditions (3.3 v)? and ?recommended operating conditions (5.0 v)? tables, deleted the conditions of t a c-grade part, t a v-grade part, t a m-grade part in the ?lqfp thermal characterist ics? table, rounded the values. in the ?reset electrical characteristics? section, replaced ?nrstin ? with ?reset ?. in the ?i/o input dc electrical characteristics? table: ?w fi : insered a footnote ?w nfi : insered a footnote in the ?low voltage monitor electrical characteristics? table: ? changed min valuev lv d h v 3 l , from 2.7 to 2.6 ? inserted max value of v lv d lv c o r l in the ?fmpll electrical characteristics? table, rounded the values of f vco. in the ?dspi characteristics? table: ? added ? t asc row ? update values of t a in the ?adc conversion characteristics? table, added ?i adcpwd ? and ?i adcrun ? rows removed ?orderable part number summary? table. 8 25-nov-2010 editorial changes and improvements. in the ?MPC5604B/c device comparison? table, changed the temperature value from 105 to 125 c, in the footnote regarding ?execution speed?. in the ?recommended operating conditions (3.3 v)? and ?recommended operating conditions (5.0 v)? tables, restored the conditions of t a c-grade part, t a v-grade part, t a m-grade part in the ?lqfp thermal characteristics? tabl e, added values concerning 64 lqfp package. in the ?medium configuration out put buffer electrical characteristics? table: fixed a typo in last row of conditions column, there was i oh that now is i ol . in the ?reset electrical characteristics? tabl e, changed the parameter classification tag for v ol and |i wpu |. in the ?low voltage monitor electrical charac teristics? table, changed the max value of v lv d lv c o r l from 1.5v to 1.15v. in the ?program and erase specifications? table, replaced ?t eslat ? with ?t esus ?. in the ?fmpll electrical characteristics? table, changed the parameter classification tag for f vco . table 45. revision history (continued) revision date description of changes how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009, 2010. all rights reserved. MPC5604Bc rev. 8 11/2010 |
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